CMOS technology has evolved such that the computer market has rapidly opened to a wide range of consumers. Today's multi-media requires at least 16 MB and preferably even 32 MB memories, which increases the relative cost of the memory system within a computer. In the near future, it is likely that computers having 64 MB and 128 MB memory will become commonplace, suggesting a potential demand for 256 Mb DRAMs and beyond. In spite of the ever increasing array sizes and lithographic difficulties that ensue, it is more important than ever to increase the yield of the semiconductor memory manufacturing process. Process engineers are constantly attempting to reduce and ultimately, eliminate or at least, mask defects. Faults that inevitably remain in the chip are generally overcome using special circuit designs, and more specifically, redundancy replacement configurations.
Conventional redundancy configurations typically revolve about a Fixed Domain Redundancy Replacement (FDRR) architecture, wherein redundancy elements are used to replace defective elements within a fixed size domain for each row and column redundancy.
Various configurations within the FDRR architecture have been successfully implemented over the years. A typical FDRR configuration, which is commonly used for low density DRAMs, is shown in FIG. 1a. Therein are depicted a plurality of spares used for replacing defective elements within the fixed size domain and which are appended to each sub-array forming the memory. Each redundancy unit (RU) includes a plurality of redundancy elements (REs), (e.g., two REs per RU are illustrated therein) which are used to repair existing faults (labeled X) within the corresponding sub-array. This scheme, labeled intra-block replacement, increases the redundancy area overhead as the number of sub-arrays increases for high density memories, since each physical sub-array is a fixed domain for replacement purposes, and domains in different sub-arrays are mutually exclusive of each other. This requires at least one or preferably two RUs in each sub-array. Thus, the efficiency of the RUs is rather poor in view of its inflexibility, which reduces the chip yield substantially when faults are clustered in a given sub-array. The above mentioned concept is embodied in a configuration described in the article by T. Kirihata et al., entitled "A 14 ns 4 Mb DRAM with 300 mW Active Power", published in the IEEE Journal of Solid State Circuits, Vol. 27, pp. 1222-1228, September 1992.
Another FDRR redundancy replacement arrangement, known as a flexible redundancy replacement configuration is shown in FIG. 1b, wherein a memory is depicted having a single array to selectively replace failing elements anywhere in the memory. In this configuration, REs within the RU can repair faults (labeled X) located in any sub-array within the memory. The advantage of this arrangement over the previously described intra-block replacement is that one section, namely, a redundancy array, having a certain number of RUs may advantageously be used to service any number of sub-arrays forming the memory. This translates into a substantial saving of real estate over the previous scheme, although it requires a substantial amount of additional control circuitry, in particular, more fuses over the previous intra-block replacement, to properly service all the sub-arrays forming the memory. More details regarding the above configurations and the various trade-off may be found in an article by T. Kirihata et al., "A Fault-Tolerant Design for 256 Mb DRAMs", published in the Digest of Technical Papers of the 1995 Symposium on VLSI Circuits, pp. 107-108; in an article by T. Sugibayashi et al., "A 30 ns 256 Mb DRAM with Multi-divided Array Structure", published in the IEEE Journal of Solid State Circuits, Vol. 28, pp. 1092-1098, November 1993; and in an article by H. L. Kalter et al., "A 50 ns 16 Mb DRAM with a 10 ns Data Rate and On-Chip ECC", published in the IEEE Journal of Solid State Circuits, Vol. 25, pp. 1118-1128, October 1990.
The Variable Domain Redundancy Replacement (VDRR) is a statistical approach that reduces the total number of fuses, while keeping good repairability. Unlike FDDR, RUs are assigned to at least two variable domains, some portions of which are mutually inclusive. FIG. 1c shows a typical arrangement for the VDDR, where a domain (C) includes four domains (B), each of which is further subdivided into even smaller sub-domains (A). When 64 faults are randomly distributed in a domain (C) which includes sixteen domains (A) and four domains (B), the probability of not finding faults in domain (A) is negligibly small. Each of the domains (A) statistically has at least one fault. The probability of less than eight faults in domain (B) that includes four domains (A) is also small. Each of the domains (B) statistically has at least eight faults. These facts imply that 32 of 64 faults within domain (C) can be effectively repaired with the combination of variable domains (A) and (B), in which 1 and 4 faults are repaired, respectively. The remaining 32 of 64 faults can be repaired using a fully flexible redundancy replacement in domain (C).
This variable domain redundancy replacement substantially reduces the redundancy overhead, in particular the number of fuses, by reducing the domain size (A) over domain (B), and domain (B) over domain (C). A potential drawback, however, exists if the faults are clustered in a non-statistical distribution. By way of example, when 64 faults are clustered within a specific domain (A), no known mechanism exists to repair them. A major drawback of this technique lies in the actual assignment of valuable real estate within the integrated circuit chip to implement the plurality of variable domains A, B and C mentioned above.
More details regarding the variable domain redundancy replacement is found in U.S. patent application Ser. No. 08/895,061, entitled "Variable Domain Redundancy Replacement Configuration for a Memory Device", filed on Jul. 16, 1997, and of common assignee.
Other related redundancy configurations, including some related to the categories listed above, are described in the following references:
U.S. Pat. No. 5,491,664 to Phelan, issued Feb. 13, 1996, describes the implementation of a flexible redundancy memory block elements in a divided array architecture scheme. This configuration has both, the memory and the redundant memory blocks, coupled to a read bus to allow the redundancy memory in one memory sub-array to be shared by a second sub-array.
U.S. Pat. No. 5,475,648 to Fujiwara, issued Dec. 12, 1995, in which a memory having a redundancy configuration is described such that when an appropriate address signal agrees with the address of a defective cell, a spare cell provided by the redundant configuration is activated to replace the failing one.
U.S. Pat. No. 5,461,587 to Seung-Cheol Oh, issued Oct. 24, 1995, in which a row redundancy circuit is used in conjunction with two other spare row decoders, wherein by a judicious use of fuse boxes, signal generated by a row redundancy control circuit make it possible to replace failing rows with spare ones.
U.S. Pat. No. 5,459,690 to Rieger at al., issued Oct. 17, 1995, describes a memory with a redundant arrangement that, in the presence of normal word lines servicing defective memory cells, enables faulty memory cells to be replaced with redundant cells.
U.S. Pat. No. 5,430,679 to Hiltebeitel et al., issued Jul. 4, 1995, describes a fuse download system for programming decoders for redundancy purposes. The fuse sets can be dynamically assigned to the redundant decoders, allowing a multi-dimensional assignment of faulty rows/column within the memory.
U.S. Pat. No. 5,295,101 to Stephens, Jr. et al., issued Mar. 15, 1994, describes a two level redundancy arrangement for replacing faulty sub-arrays with appropriate redundancy elements.
Practitioners of the art will readily recognize that each of the above solutions described above suffer from a major drawback, i.e., they all require setting aside a substantial amount of chip real estate to provide the redundancies necessary to repair faults within the memory. Each of the aforementioned techniques reserves one or several blocks (or units) containing each either a fixed or a variable number of redundancy elements. Sometimes these units are assigned to each primary array in the memory, sometimes the units are not yet assigned and are clustered at the bottom of the chip, requiring in turn a substantial amount of control circuitry to manage the assignment of the units to the individual memory arrays forming the memory device. In all instances, though, these redundancy groups, units, elements, and the like are built in the IC chip alongside with the memory device(s).
Practitioners of the art will further recognize that the prior art previously discussed has been described mainly in terms of DRAMs (Dynamic Random Access Memory), although the above configurations and/or architectures are equally applicable to other types of memory devices, such as SRAMs, ROMs, EPROMs, EEPROMs, Flash RAMs, CAMs, and the like. However, in addition to memory devices, today's chips may also contain only logic, or a mixture of logic and memory (i.e., embedded arrays). Since all types of integrated circuits are constantly designed with an ever increasing density, the presence of faults is a universal problem which affects all types of integrated circuit chips: logic, memory, programmable logic arrays (PLAs), ASICs, etc.